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lxp730 multi-rate dsl framer january 1999 data sheet general description features revision 2.0 refer to www.level1.com for most current information. mdsl interface slip buffer recovered clock shared time slot interchange (tsi) pcm-bus interface async data port interface (adpi) mx elastic store receive framer moh dx moh mx stuff codec interface all digital pll (adpll) dx elastic store registers overhead serial i/o (osio) interface clock generation and distribution microprocessor interface the lxp730 is a multi-purpose digital subscriber line (dsl) framer which complements the level one sk70725/21 enhanced mdsl data pump (emdp) to provide seamless transport of data and voice signals over one or more dsl datapaths. the lxp730 in combination with the emdp chipset is optimized for use as a framer or i/o interface device for the following applications: ? digital pair gain systems ? ethernet modems ? t1/e1 fractional transport systems ? videoconferencing systems ? simultaneous data - voice transport systems ? wireless base station access systems the lxp730 provides the basic functions required of a dsl framer: ? synchronization of external data streams to the dsl line ? multiplexing and demultiplexing of independent data streams for voice and data ? loopback of payload data at the dsl interface ? creation, insertion, and recovery of the mdsl overhead (moh) structure, performance monitoring, and message transport required in a dsl system with a capacity of up to 32 kbps ? supports two input/output data streams simultaneously ? slave mode: external clock determines the rate at which data will be transferred to and from the framer ? master mode: clock derived from received dsl clock or external oscillator ? single part architecture allows one chip to be used economically in both central and remote locations ? supports systems with point-to-point architectures ? alternate hardware control mode (hwc) for operation without an external microprocessor applications lxp730 block dia g ram )
lxp730 multi-rate dsl framer 2 ) pin assignments and signal descriptions figure 1: lxp730 pin assignments table 1: lxp730 pin descriptions pin symbol type 1 description 1, 9, 16, 33, 48 vcc _ power supply. 10, 17, 32, 49, 64 gnd _ ground. 28 data0/ crc_error di/o, do data0. mpc mode/ crc_error. flag hwc mode, indicates an error was detected in the previous frame. 29 data1/febe di/o, do data1. mpc mode/ febe. flag hwc mode, indicates the other side of the dsl link encountered a crc error. 30 data2/ link_active di/o, do data2. mpc mode/ link_active. hwc mode, indicates that the dsl link is active and ready to transport data. 31 data3/run- stop di/o, di data3. mpc mode/ run-stop. hwc mode, set to low to activate the dsl link, edge triggered input. 34 data4/ frmsync15 di/o, do data4. mpc mode / frmsync15. hwc mode, frame sync pulse, channel 15. 1. ai = analog input; ao = analog output; di = digital input; do = digital output; nc = no clamp. pad will not clamp input in th e absence of power; pu = input contains pull-up; pd = input contains pull-down; i/o = input/output; od = open drain output; to = tri-state o utput. gnd osdo osdock osdi osdick addr0 addr1 addr2 addr3 addr4 addr5 data0 data1 data2 data3 gnd 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 vcc rdata quatclk tdata osof bitclk int ale/htu_sel ()/hwc rd r/w( )/hwc wr cs/hwc data7 data6 data5 data4 vcc gnd test1 frmsync4 frmsync5 frmsync6 frmsync7 frmsync8 motel/hwc reset frmsync9 frmsync10 frmsync11 frmsync12 gap_clk osif gnd 1 7 18 19 2 0 2 1 2 2 2 3 24 2 5 2 6 2 7 2 8 2 9 3 0 3 1 3 2 64 63 62 61 60 59 58 57 56 55 54 53 52 5 1 50 4 9 64-pin lqfp vcc cclk/tclko cdato cdati frmsync1 frmsync2 frmsync3 mclk vcc gnd test2 pdi/t1e1l/z 1 pfrm/frmin/z 0 pclk/tclki pdo/t1e1o/z 2 vcc
lxp730 pin assignments and signal descriptions 3 ) 35 data5/ frmsync16 di/o, do data5. mpc mode / frmsync16. hwc mode. frame sync pulse, channel 16. 36 data6/ frmsync17 di/o, do data6. mpc mode / frmsync17. hwc mode. frame sync pulse, channel 17. 37 data7/ frmsync18 di/o, do data7. mpc mode / frmsync18. hwc mode. frame sync pulse, channel 17. 22 addr0/ frmsync13 di, do addr0. mpc mode/ frmsync13. hwc mode. frame sync pulse, channel 13, output. 23 addr1/n1 di addr1. mpc mode/ n1. dsl rate select, hwc mode. 24 addr2/n2 di addr2. mpc mode/ n2. dsl rate select, hwc mode. 25 addr3/n3 di addr3. mpc mode/ n3. dsl rate select, hwc mode. 26 addr4/n4 di addr4. mpc mode/ n4. dsl rate select, hwc mode. 27 addr5/ frmsync14 di, do addr5. mpc mode /frmsync14. frame sync pulse, channel 14, output, hwc mode. 57 motel/hwc di motel/hwc. set high for motorola mode, set low for intel mode, micro processor control (mpc) mode, input /hwc. pull high for hwc mode, input. 39 r/w(wr )/hwc select di r/w(wr ). r/w for motorola interface, wr for intel interface /hwc select, set low for hwc mode. 40 (rd )/hwc select di (rd ). unused for motorola interface, rd for intel interface /hwc select, set low for hwc mode. 38 cs /hwc select di cs . chip select, hwc select, set low for hwc mode. 41 ale/htu_sel di ale. address latch enable for intel interface, mpc mode, input /htu_sel. htuc/htur select, high for htuc, low for htur, hwc mode, input. 42 int do int . interrupt output. programmed by setting bits in the int_en register. 56 reset di reset . active low input. all registers revert to their default values. 8mclkdi mclk. master clock. 4 cdati di cdati. codec data in. 3 cdato to cdato. codec data out, tri-state. 2 cclk/tclko to cclk. codec clock, nominal 2.048 mhz, tri-state. / tclko. transport clock for t1/e1: 1.544 mhz or 2.048 mhz clock derived from line rate. 5frmsync1/ frmout do frmsync1. frame sync pulse, channel 1, output. /frmout. frame out, for t1/e1 application, output. 6 frmsync2 do frmsync2. frame sync pulse, channel 2, output. 7 frmsync3 do frmsync3. frame sync pulse, channel 3, output. 62 frmsync4 do frmsync4. frame sync pulse, channel 4, output. 61 frmsync5 do frmsync5. frame sync pulse, channel 5, output. 60 frmsync6 do frmsync6. frame sync pulse, channel 6, output. table 1: lxp730 pin descriptions C continued pin symbol type 1 description 1. ai = analog input; ao = analog output; di = digital input; do = digital output; nc = no clamp. pad will not clamp input in th e absence of power; pu = input contains pull-up; pd = input contains pull-down; i/o = input/output; od = open drain output; to = tri-state o utput.
lxp730 multi-rate dsl framer 4 ) 59 frmsync7/ sdock do frmsync7. frame sync pulse, channel 7, output. /sdock. serial data out clock, adpi serial mode, output. 58 frmsync8/ sdo do frmsync8. frame sync pulse, channel 8, output. /sdo. serial data out, adpi serial mode, output. 55 frmsync9 sdick do frmsync9. frame sync pulse, channel 9, output. /sdick. serial data in clock, adpi serial mode, output. 54 frmsync10/ sdi do, di frmsync10. frame sync pulse, channel 10, output. / sdi. serial data in, adpi serial mode, input. 53 frmsync11 do frmsync11. frame sync pulse, channel 11, output. 52 frmsync12/ pdoe do frmsync12. frame sync pulse, channel 12, output. / pdoe. pcm data output enable, control for external pcm interface buffer, output. enabled by bit-3 of register 23h. 51 gap_clk do gap_clk. gapped clock, n x 64 khz recovered from dsl for optional external adpll, output. output is high when option not selected. 63 test1 di test1. factory test pin 1, input; should be tied to gnd. 11 test2 di test2. factory test pin 2, input; should be tied to vcc. 21 osdick do osdcki. overhead serial data in clock, output. 20 osdi pu osdi. overhead serial data in, input. 19 osdock do osdock. overhead serial data out clock, output. 18 osdo do osdo. overhead serial data out, output. 44 osof do osof. overhead serial output flag, output. indicates the first bit of osio output frame. 50 osif do osif. overhead serial input flag, output. indicates the first bit of osio input frame. 45 tdata do tdata. transmit data, output. connect to sk70725. 47 rdata di rdata. receive data, input. connect to sk70725. 46 quatclk di quatclk. quaternary alignment clock, input. connect to sk70725. 43 bitclk di bitclk. bit clock, input. connect to sk70725. 13 pfrm / frmin / z 0 di,do, di pfrm. pcm frame pulse: input for pcm slave, output for pcm master. alignment signal for the first time slot for both pdi and pdo. /frmin. frame in, for t1/e1 application, input. /z o . bit zero of the 3-bit word used to specify the number of z bits in the hardware mode, input. 12 pdi / t1e1i / z 1 pu,di, di pdi. pcm data in, input. /t1e1i. t1 or e1 input data, input. / z 1 . bit one of the 3-bit word used to specify the number of z bits in the hardware mode, input. 15 pdo / t1e1o / z 2 to,to, di pdo. pcm data out, tri-stateable output. /t1e1o. t1 or e1 output data, tri- stateable output. / z 2 . bit two of the 3-bit word used to specify the number of z bits in the hardware mode, input. 14 pclk/tclki di/o pclk. pcm clock: input for pcm slave, output for pcm master. /tclki. transport clock in, for t1/e1 application, 1.544mhz - t1, 2.048mhz - e1, input. table 1: lxp730 pin descriptions C continued pin symbol type 1 description 1. ai = analog input; ao = analog output; di = digital input; do = digital output; nc = no clamp. pad will not clamp input in th e absence of power; pu = input contains pull-up; pd = input contains pull-down; i/o = input/output; od = open drain output; to = tri-state o utput.
lxp730 functional description 5 ) functional description lxp730 nx64 framer the lxp730 is designed to multiplex/demultiplex two payload sources to/from a dsl stream, and add/recover overhead data for link control. several popular interfaces are provided to support a variety of applications. the two major categories of payload supported are synchronous (i.e. voice-frequency data - pcm) and asynchronous (i.e. digital data - packet/cell). the lxp730 supports n x64 kbps channels in the dsl with n = 4 to 18. the lxp730 consists of the following functional blocks as shown on page 1: ? time slot interchange (tsi) ? pcm-bus interface ? codec interface ? t1/e1 interface ? asynchronous data port interface (adpi) ? microprocessor interface ? overhead serial i/o (osio) interface ? sk70725/sk70721 (mdsl) interface ? all digital pll (adpll) ? clock generation and distribution the terms local and remote are used in this document to designate the two ends of a dsl link. the local is usually the master in that it initiates the link startup and can control the actions and configuration of the remote. there are several equivalent nomenclatures in the telecom industry. some of these are, respectively: co and cpe, or htu-c and htu-r, or ltu and ntu. the following is a description of the lxp730 functional blocks. time slot interchange (tsi) the time slot interchange (tsi) is the central module of the lxp730 nx64 framer. the tsi maps payload to the available dsl n-channels for transport across the loop. the tsi uses register settings to select time slots to map into the n mdsl channels. the total number of available payload channels is n and is set by the n_mdsl register (00h), with selected valid values from 4 to 18. each of the 18 nx registers (01h -012h) is used to select the payload source, and if applicable, the pcm time slot assigned to the registers corresponding mdsl channel. in the mx direction (from the tsi to the mdsl interface), the tsi multiplexes the payload sources into the mx elastic store (mx es). the payload and overhead are multiplexed into the dsl stream for loop transport. in the dx direction (from the msdl interface to the tsi), the tsi reads from the dx elastic store (dx es) and demultiplexes the loop data into its payload data sources. synchronous payload sources are typically 8-bit serial time slots, cascaded together with each source repeating every 125 sec (i.e. 8 khz). a framing pulse, separate from the data signal, signifies the start of a frame. a 2.048 mbps data stream has 32 time slot sources, while a 1.544 mbps data stream has 24 time slot sources plus one extra bit for framing. when the pcm or codec interfaces are running, the framing pulses are used by the tsi to initialize operation to the mx es. the mx es and dx es have triple buffering schemes that prevent the loss of data. the pcm/codec interfaces typically produce high speed data bursts while the mdsl interface runs at a slower though irregular rate. asynchronous data is typically a sequence of bytes which have no explicit timing relationship between them. asynchronous data port interface (adpi) bytes may be inserted into payload slots that are not carrying pcm data. adpi bytes are inserted into the dsl stream in the order they are received from the interface. channel blocking on a mdsl channel is achieved by setting the ch_cfg bits in the nx register to 01. the transported value for that mdsl channel will be the one stored in the idle register. the tsi uses the mclk clock to synchronize to the various interfaces. the mclk frequency must be at least three times the highest interface clock frequency for the tsi to function properly. there are other considerations to select the operating frequency of mclk when using the internal adpll.
lxp730 multi-rate dsl framer 6 ) pcm-bus interface the lxp730 provides a generic interface for common pcm-bus configurations and can either be master or slave to these pcm busses. some of the key features that allow flexibility are: ? clock at 1x or 2x the data rate ? programmable number of bytes per frame; 8, 16, 32, 64 ? programmable clock and frame pulse polarities these features allow interfacing to standard pcm styles such as: st, iom, iom2 (see figure 8 for circuit) and chi. the data rates can range from 256 kbps to 4096 kbps. the clock rates can range from 256 khz to 8196 khz. the range of permissible pcm time slots are 0 to 31 for a 2.048 mbps backplane and 0 to 63 for a 4.096 mbps backplane for a total number of time slots up to the maximum number n. pcm time slots must be assigned in ascending order to mdsl channels. the value set in the ts-bits in the nx registers select the pcm timeslot to go into the xth mdsl channel. there is a limitation of the disparity allowed between the pcm clock and the bit_clk. for n = 4, the pcm bit rate cannot exceed 2 mbps. to use a 4 mbps pcm interface the nmdsl setting must be at least 6 channels. on these busses, the input and output data streams are synchronized to the same clock. a slip buffer is present on the receive side to accommodate the differences in the pcm clock frequencies of the two ends of the mdsl line. the slip buffer is two frame lengths long. the buffer will empty if the pcm clock is reading data out of the slip buffer faster than the tsi is writing into it. when the last bit for the frame has been read and there is not another byte from the next frame to clock out, the read pointer is set back to the beginning of the current frame and repeated. the other slip situation occurs when the tsi is writing data faster than the pcm is clocking it out. when the write pointer gets close to the read pointer that hasnt finished a frame, then the read pointer is allowed to finish the current frame and then is advanced to skip the next frame. the slip buffer may be bypassed by setting the sbbp bit, (bit 0, in the pcm_cfg1, register). slip occurrences are detected and signalled in the interrupt status register. normally the lxp730 pcm bus is configured as a slave in the local unit, while the remote lxp730 pcm bus can be either configured as slave or master off the pcm bus. when the remote lxp730 is in pcm slave mode, the slip buffers accommodate the differences in the two pcm clocks. when the remote lxp730 is in pcm master mode, the pcm clock and frame pulse are derived from the receive dsl clock using the internal adpll to provide loop timing to prevent the slip action from occurring. the pcm bus timeslot assignments to the dsl channels may be altered while the dsl link is active. the nx registers can be changed without interfering with other nx registers and the effect of their settings. the pdo pin is tri-stated except during programmed time slots. the pfrm pulse defines the start of a pcm frame. the number of pcm time slots per frame is variable from 4 to 64. this is programmed by setting the six maxpchn bits in, the pcm_cfg2 register, with the value n-1 number time slots. pcm selection for a mdsl channel is accomplished by setting the ch_cfg bits in the nx register to 10 (binary). codec interface the lxp730 primarily supports the combo codec i style devices. the lxp730 codec interface is programmable to allow the use of other codec type devices that require a positive frame pulse. the lxp730 provides a separate set of pins for this interface allowing simultaneous operation with a pcm bus with the following characteristics: ? short frame positive sync pulse ? clock at 1x or 2x the data rate ? programmable number of bytes per frame in mpc; 8, 16, 32, 64 the data rates can range from 256 kbps to 4096 kbps. the clock rates can range from 256 khz to 8196 khz. under hwc mode, the number of bytes per frame is limited to 32. the input and output data from the tsi are connected to the codec cdati and cdato pins for the appropriate time slot. the cdato pin is tri-stated except during programmed time slots. only twelve (12) codecs are supported in the mpc mode. the lxp730 is always the master on the codec bus. the lxp730 can be configured to derive the clock and frame pulse from either mclk (in codec master mode) or from the dsl clock using the internal adpll (in codec slave mode). one lxp730 of the dsl link must be in the master codec mode and the other in the slave codec mode.
lxp730 functional description 7 ) the lxp730 generates the codec clock and the framing pulses for eighteen (18) codecs from the selected reference. selecting codec timeslot 0 in an nx register corresponds to frmsync1, 1 to frmsync2, etc. in hwc mode, the frmsync pins are automatically assigned with the programming of the nx pins. the number of codec time slots per frame is variable from 4 to 64. this is programmed by setting the six maxcchn bits in the cod_cfg register (22h) with the value n-1 number time slots. codec selection for a mdsl channel is accomplished by setting the ch_cfg bits in the nx register to 00 (binary). t1/e1 interface the lxp730 supports t1/e1 framer interfaces by using a hybrid of the pcm and codec interfaces to transport pleisiochronous data. the pcm interface is used in its slave mode to connect a t1/e1 framer and its txdata (t1e1o), rxdata (t1e1i), rxclk (tclki) and framepulseout (frmin). the slip buffer must be in the bypass mode. the codec interface is used in its slave mode to derive the framepulsein (frmout) and txclk (tclko) to the t1/e1 framer. the derived t1/e1 frmout tracks the mdsl frame rate from the dsl, and in cases where framing is lost, the dx tracking circuits slowly reacquire to prevent a drastic change in the output frame frequency. the pcm and codec sections must each be configured through registers to handle the t1/e1 pleisiochronous data. for t1, only n =12 or fractional t1 is supported. in t1, the only workable value for the pcm_cfg2 register is 98h. the mx t1 f-bits must be part of the data stream coming from the external t1 framer. the 12 unused dx t1 time slots are filled with the value programmed in the idle register if the tfi bit (bit 0) is set to 0. key features of the t1e1 interface are: ? framer interfaces: ds2141and ds2143 ? data rates: 1544 and 2048 kbps ? clock rates: 1544 and 2048 khz asynchronous data port interface (adpi) the lxp730 supports a serial method for the asynchronous data port interface (adpi). the adpi is available only in the mpc operating mode. mdsl channels are programmed for adpi by setting the ch_cfg bits to 11 (binary) in the desired nx register. the operation of the adpi is mutually exclusive with the lxp730 codec frame sync pins (frmsync7-10). the serial adpi mode provides separate pins for data in, data out, clock-in and clock-out. this is compatible with the bit operation protocol (bop) for hdlc devices. the lxp730 controls both of the clocks, and therefore, the data flow. the lxp730 moves the bits in and out in 8-bit groups. the maximum clock rate for the bit-to-bit transfer is set by the sapclkdiv bits in the fifo_misc register. this allows the clocks to run at mclk ? 2 or slower. the groups of clock pulses will be gapped due to the availability of bit positions in the dsl data stream. overhead interface the lxp730 provides two options for the interface to insert and receive overhead data for the link: via an external serial interface or through the microprocessor register interface. the data can either be user defined or partially predefined as described in mdsl overhead definition on page 11. the overhead channel is used for signalling, status flags, loopback control, and diagnostic messaging between the local and remote ends of a mdsl link. the lxp730 provides the transparent channel for the overhead data and does not interpret the protocol operation. the f-bits in the fractional t1 mode are not part of the overhead. overhead serial i/o (osio) the osio interface is the default overhead access for both the mpc and hwc operational modes. the serial interface provides six separate pins for data in (osdi), data out (osdo), clock-in (osdick) clock-out (osdock), start flag in (osif), and start flag out (osof). the use of the first four pins is compatible with the bit operation protocol (bop) for hdlc devices. the two flag pins (osif and osof) provide indications of the start of a mdsl frame and may used with custom overhead handling devices. the flag signals are coincident with the first overhead bit in the mdsl frame.
lxp730 multi-rate dsl framer 8 ) the lxp730 controls both of the clocks, and thus, the data flow. the clocks will be gapped due to the availability of bit positions in the dsl data stream. the osio may be disabled in the mpc mode by setting the par/ser bit in the ovrhd_sel register (24h). osif and osof will continue to operate. the defined bits (except the indc_r bit) go to the microprocessor interface registers. the undefined bits (plus the indc_r bit) go to the osio interface. this allows a separate transport for hdlc devices while maintaining dsl performance monitoring. mdsl overhead microprocessor interface the mdsl overhead microprocessor interface mode uses internal registers to provide the access to insert and receive overhead data for the link. the par/ser bit must be set to access the contents of the overhead and z bit registers. interrupts may be used to synchronize the contents with the mdsl link. the data can either be user defined or partially predefined as described in mdsl overhead definition on page 11. microprocessor writes to defined bits have no effect, with the exception of the indc_r bit. the registers for the oh and z bits are double buffered for both the mx and dx sections. when the ohmx bit is set in the int_stat, 3fh, register, the values in the user assessable mx registers are latched into an internal set of registers, and then serially shift throughout the frame. the user has a nominal 6 ms to update the mx registers before they are latched again for transport. likewise, the dx registers hold their values until the ohdx bit is set, then the overhead data from the latest frame is available. the user again has a nominal 6 ms to read the dx data before it is over written. mdsl interface each lxp730 device works directly with one sk70725/21 data pump chip set. the sk70725/21 chip set must be in mode 0 to work with the lxp730. refer to the sk70725/ 21 data sheet for details. the lxp730 provides tdata to the data pump and accepts quatclk, bitclk and rdata signals from the data pump. the framer supports line data rates from 272 kbps to 1168 kbps. table 2 shows some of the common even-numbered transport, nominal line rates and the number of bits per frame. odd numbered n values may also be used. the first value in the bits/frame column is the number of bits in an unstuffed frame, and the second value is with stuffing. mdsl frame periods are a nominal 6 ms regardless of the nominal line rate. the line rate is calculated as n x 64 kbps + 16 kbps, where n is the number of 64 kbps channels to be transported. the 16 kbps is the total overhead provided by the mdsl trans- port system. the 16 kbps holds true as long there is one z bit per block as described in mdsl frame format on page 12. the lxp730 supports up to eight z bits per block, but when greater than one, the overhead rate increases. this causes the line rate to increase accordingly. the equation to calcu- late the dsl line rate is as follows: line rate (kbps) = 8[z + 1 + (n x 8)] the lxp730 will scramble payload data, but pass the sync word in the clear. in the local mode, the lxp730 uses the following scrambling polynomial: x -23 + x -5 + 1, in the remote mode the scrambling polynomial is: x -23 + x -18 + 1. in transparent mode, the lxp730 uses the quat alignment signal (quatclk) from the data pump to align the sign and magnitude bits in both the transmit and receive directions. the overhead bits are described in mdsl overhead definition on page 11. before routing the data to the descrambler, the lxp730 will invert the sign bits of the received data stream, if the detected frame sync word has inverted sign bits. table 2: common transport & line rates data rate (kbps) nominal line rate (kbps) 64 kbps channels (n) bits/ frame 256 272 4 1630/1634 384 400 6 2398/2402 512 528 8 3166/3170 640 656 10 3934/3938 768 784 12 4702/4706 1152 1168 18 7006/7010
lxp730 functional description 9 ) the mdsl interface provides loopback of tdata, bypassing the external rdata. loopback is activated by setting the dsl_lb bit in the ovrhd_cfg register (24h). this routes the 64 kbps channels and mdsl overhead (moh) from the mx section to the dx section. when using an external loopback configuration, such as felb in the sk70725, it is necessary to switch the dx de- scrambling polynomial to the mx polynomial. the descrambling polynomial is inverted by setting the remote_lb bit of the fifo_misc register (17h). the bitclk and quatclk control the transfer of data from the mx to the dx section. all digital pll (adpll) the lxp730 adpll is necessary for clock recovery and to control output jitter and wander produced in the dsl environment. the adpll uses mclk to drive the nco circuitry, while the reference frequency comes from the received dsl frame rate that has a nominal 6 ms period. adpll performance: the selection of k loop the performance of the adpll is user programmable via a register. as shown in table 3, the 5-bit value, k loop , in pllctl3 register controls the lock time and the bandwidth of the adpll. the lock time is the amount of time required for the adpll to acquire and synchronize to the input mdsl signal. the bandwidth of the adpll determines the jitter rejection characteristics of the adpll. the bandwidth and lock time are inversely related: bw = 3/t lock . kloop is a 5 bit control field found in register pllctl3 (address 1d hex, 29 dec). the register bits are used to select a constant (kloop_value) that controls the loop bandwidth. the bandwidth of the loop filter is determined from the selected kloop_value and the frequency of mclk. loop bandwidth (bw) is calculated as follows: adpll center frequency: the computation of cfreq the center frequency of the adpll is set by an 18-bit unsigned fractional number, cfreq(17:0). this value is programmed in pllctl1, pllctl2, and pllctl3. cfreq(17:0) is the ratio of the numerically controlled oscillator (nco) and mclk, and is shown below. the 2 18 is the normalizing factor to express it in integer notation. it must then be converted to hexadecimal to load into the cfreq register. the output of the nco is divided by 2 before being provided to the clock multiplex circuitry and the optional prog_div block. this must be taken into account when deciding upon the frequency for the nco. the nco/mclk ratio should be set to a value greater than or equal to 0.5 but less than 0.98. this ensures that there will be the maximum number of bits of accuracy for the nco to generate the frequency. the ratio of 0.5 normalized with 2 18 is 131072 or in hexadecimal, 20000h. this is the smallest recommended value. calculation of cfreq table 4 list values for: cfreq(17:0), programmable divider, and nco frequency for a mclk of 16.384mhz in several configurations. table 3: k loop values register bits kloop_value 00000 pll freeze 00001 2 0 00010 2 -1 00011 2 -2 00100 2 -3 ... ... 11111 2 -30 bw (3db) = kloop_ va lue mclk 3.89e-5 hz cfreq round ncofreq 2 18 () mclk ----------------------------------------------- - =
lxp730 multi-rate dsl framer 10 ) clock generation and distribution the lxp730 has a flexible clock generation circuit as shown in figure 2. the clocks for the pcm and codec interfaces can be an independent external input, a division of mclk, a division of the adpll output, or the adpll output as selected by the pcm configuration 1 register (pcm_cfg1) and the codec configuration register (cod_cfg). the pcm port is considered to be in slave mode when its clock source is the external pin. the pcm frame pulse is also sourced from its external pfrm pin when the clock is configured as such. the pcm port is in master mode for the other three settings. the pcm frame pulse is derived from the internal pclk and driven out on the pfrm pin. the codec port initially has the cclk pin tristated until it is configured as an output by setting the cclk_oe bit in the misc_ctl register. it is never an input. the external source for the codec clock is the pclk pin. this allows simultaneous use of the pcm and codec interfaces with the pcm bus providing the clock and allowing mclk to be some other frequency that may not be suitable to divide down for the codecs. the adpi clock is not derived from the circuit shown in figure 2, but rather comes from the tsi module. the tsi keeps track of opportunities to transmit bytes into the dsl frame and creates a burst of eight pulses to clock a byte of data to insert in the mx direction. the tsi unloads data from the dx dsl direction and also creates a burst of eight pulses to clock a byte of data to the external device con- nected to the adpi interface. the burst frequency of the adpi clocks is derived from mclk and can be adjusted by the sapclkdiv (bits 6 & 7, in register 17h, fifo_misc). figure 2: clock generation and distribution table 4: typical adpll register settings, mclk = 16.384mhz pcmclk output (mhz) #b pcm #b dsl nco frequency (mhz) prog_ div ncofreq/ mclk cfreq(17:0) 1.544 24 12 pcmclk 8 4 0.754 0x30400 2.048 32 18 pcmclk 4 2 0.5 0x20000 1.152 18 18 pcmclk 8 4 0.5625 0x24000 0.896 14 14 pcmclk 16 8 0.875 0x38000 0.768 12 12 pcmclk 16 8 0.75 0x30000 0.256 4 4 pcmclk 32 16 0.5 0x20000 nco ? 2 pcm clock select programmable divider (1e: 7 - 0) codec clock select pcm port (20: 6 - 5) codec port (22: 7 - 6) mclk (pin 8) pclk (pin 14) divider clock select
lxp730 functional description 11 ) modes of operation microprocessor control (mpc) mode the microprocessor control (mpc) mode provides access for a microprocessor to configure and control the operation of the framer. the lxp730 provides an 8-bit data bus for the purpose of reading and writing internal registers. the registers are used to configure framer settings, to read and write the mdsl overhead bits and to configure interrupts and other run-time operational functions. the microprocessor access circuits support both motel (motorola/intel) microprocessor interfaces. a chip select signal activates the interface between the device and the microprocessor. in the motorola mode, the lxp730 supports the r/w and cs signals. the motorola signal ds is not used in this mode. in the intel mode, the lxp730 supports the cs , ale, wr and rd signals. in the intel mode, the data pins conform to the intel style address/data (ad) functionality. the address is presented to the ad pins and internally latched with ale, then the data is either read from or written to the device. ale may be held high for non-multiplexed address and data operation in the intel mode for use of the wr and rd signals. one interrupt pin is provided. registers are provided for enabling/disabling the interrupts and monitoring the status of the interrupt signals. in the mpc mode, both the pcm and codec/data port interfaces may be used simultaneously. the assignment of the 64 kbps timeslots from the interfaces to the dsl is controlled by the tsi (time slot interchange) block. this feature allows data from two different sources to be transported over the dsl. hardware control (hwc) mode this mode provides an operational method to run only the codec and osio interface without a microprocessor. pins are provided to select the number (n) of 64 kbps channels to be transported. the following error/status flags output pins are provided: link_active, crc_err and febe. reset , htuc/hutr and run-stop control signals (input pins) are provided. these pins are shared with the microprocessor mode pins. the hwc mode is selected by pulling the wr , rd , cs and ale pins low and the motel pin high. only the codec and osio interfaces are accessible in the hwc mode. the first n codec frame sync pins are active in sequence from 1 to n. as shown in table 5, pins n1 through n4 are used to select the quantity of codecs supported and to select the proper mdsl frame format. the n0 pin is not used since n is always an even number in the hwc mode. the codec interface runs only at the 2.048 mhz 1x clock in the hwc mode. mdsl overhead definition the mdsl overhead bits do not carry any payload values but are used for exchanging messaging and signalling information between the two ends of the dsl link. the overhead bits are divided into two categories; oh and z bits. the oh bits are defined in both the etsi ert/ets-152 and ansi t1e1.4/94-006 standards. these usually have specific definitions. in the lxp730, the oh bits may be partially defined, according to the standards, or totally user definable which is referred to as transparent mode. the lxp730 supports dsl oh bits in four modes: 1. transparent and register accessible. 2. transparent and osio accessible. 3. partially predefined and register accessible. 4. partially predefined and osio accessible. the reset default overhead mode is number 4. the modes are selected by setting bits 7 and 6 of register 24h, ovrhd_cfg. in the hwc mode some of the pre-defined bits status is routed to external status pins, i.e. crc_error, febe, link_active. table 5: pin settings for hwc dsl line rates number of mdsl channels pin n4 n3 n2 n1 4 0001 6 0010 8 0011 10 0100 12 0101 18 1000
lxp730 multi-rate dsl framer 12 ) predefined overhead pre-defined bit-fields support: frame sync word, stuff-bits, los , crc-6 , febe , indc_r , f bits and user defined overhead bits. in this mode the user may write to the corresponding bits in the mxoh registers, but the lxp730 will ignore them and insert the predefined bits into the bit stream. the frame sync word (fsw) bit pattern consists of the following 14 bits in order from left to right: (10101000001000), this generates the +3 +3 +3 -3 -3 +3 -3 quat valued sync waveform on the mdsl. other valid sync patterns are the time-reversed, sign bit inverted, and the time reversed sign bit inverted patterns shown in table 6. the generation and detection of the fsw is automatic. detection of a frame that has an inverted sign bit causes the mdsl block to invert the sign bits of the data stream before it is sent to the descrambler. stuff-bits are normally either four (4) bits or zero (0) bits immediately before the sync word of the next frame. the stuffing decision circuit is located in the mdsl interface block. a special mode fixes the stuff bits at two per frame for applications that require fixed timing such as connections from a wireless base station to its remote sites. this is controlled by bit 0 in register 17h, fifo_misc. the los bit is used to notify the other side of the dsl of a loss of source from the pcm bus. crc-6 bits are calculated at the transmitter for each frame and sent during the following frame. at the receiver the crc-6 is calculated on the received frame, stored and then compared with the crc-6 value received in the following frame. sync word bits, stuff bits and crc-6 bits are the crc-6 calculation. the febe bit is set in the mx side to the other mdsl unit when a crc-6 error detected is in the dx side. the indc_r bit is set in the mx side to notify the other mdsl unit that it is ready to receive transport data. z bits the first three z bits in an mdsl frame are reserved for loop id for multi-loop dsl systems by the etsi standard. all other z bits are user defined. one common use is to send the time slot configuration from the local unit to the remote unit. the z bits may either accessed through the registers or the osio interface. this is controlled by the z_ctl bit in register 23h, misc_ctl. when oh and z bits both go through the osio, they go in order as listed in the frame structure in table 7. for example: if transparent oh and z bits all go through the osio, then the order for an mdsl frame is 2 oh bits, 12 z bits, 10 oh bits, 12 z bits, 10 oh bits, 12 z bits, 10 oh bits, 12 z bits. switching to oh predefined, the corresponding predefined oh bits would not appear at the osio and there would be a gap at those time locations. in hwc mode all the z bits and the user definable oh bits go through the osio. when the lxp730 is in fractional t1 mode, z bits are part of the payload and not accessible, otherwise they are accessible in the z bit registers. mdsl frame format the lxp730 has a transport frame format that adjusts automatically with the n setting. the overall structure remains constant while adjusting the number of time slots within the payload blocks. table 7 and figure 3 shows the overall frame format. table 6: mdsl frame sync word (fsw) patterns type pattern bits quat value normal 10101000001000 +3 +3 +3 -3 -3 +3 -3 time-reversed 00100000101010 -3 +3 -3 -3 +3 +3 +3 inverted-sign-bit 00000010100010 -3 -3 -3 +3 +3 -3 +3 inverted-sign-time-reversed 10001010000000 +3 -3 +3 +3 -3 -3 -3
lxp730 functional description 13 ) the frame is made up of a sync word, followed by alternating sets of mdsl overhead bits and groups of data blocks. the final element of each frame is a section set aside for stuffing, used to synchronize payload with dsl framing where required. each data block contains [z + (n 8)] bits. the blocks are transmitted in groups of 12. in t1 mode z=1 and the 12 z-bits per block group are reserved for framing/signalling and are referred to as f -bits. in all other modes they are user accessible overhead bits known as z -bits. the frame structure matches the 784 kbps structure adopted by t1e1 and etsi. for n=18 and z=1, the frame format follows that of an 1168 kbps hdsl system compliant with etsi standards. startup operation this description applies to the mpc mode for the lxp730. typically the user sets most of the desired register values and then sets the run bit in register 24h, ovrhd_cfg. at this point the mx side of the framer is sending data to tdata and the dx side is looking for the fsw. the next step requires clearing of int_stat register by writing oxff to it. it must be ensured that the sk70725/21 chipset is in either master or slave mode as needed. the sk70725/ 21 chipset needs to be reset and the activate bit toggled in the sk70725/21 chipsets. the main control register has to be toggled. in master mode, the sk70725/21 will start the activation sequence with the slave responding. in a few seconds the data pumps will have set their filter and echo coefficients and switch to transparent transport mode. there is an additional setup to consider when the lxp730 is in pcm slave mode and n=18. if there is no clock run- ning, then there is a halt condition when 18 pcm time slots are selected. the work around is to temporarily set the last two of the nx registers to codec configuration, then set the run bit. once that is done then change the nx registers back to the desired pcm configuration. figure 3: frame format for n=12 table 7: mdsl frame format description number of bits sync word 14 moh 2 b1-b12 [ z + (n 8)] 12 moh 10 b13-b24 [ z + (n 8)] 12 moh 10 b25-b36 [ z + (n 8)] 12 moh 10 b37-b48 [ z + (n 8)] 12 stuff 0 or 4, typ avg 2 mdsl block (784k): ts1 ts2 ts0 ts4 ts5 ts8 ts7 ts3 ts6 t11 t10 ts9 8 8888888888 8 z oh blks 1 - 12 mdsl frame (784k): synch oh oh blks 13 - 24 oh blks 25 - 36 stuff blks 37 - 48 6 msec 14 2 1164 10 1164 10 1164 10 1164 0 / 4
lxp730 multi-rate dsl framer 14 ) the dx side of the lxp730 will go to active upon receipt of two successive mdsl frames. when this first occurs, the active bit in int_stat is set, but will stay reset once it is cleared until the framer goes to inactive and back to active again. the active bit is edge triggered. the dslactive bit in crc_febe_st is level triggered or sticky. once the dsl is active, no support is required to keep it operating. at this point there are basically two tasks to perform: 1) monitor for error conditions, 2) use the overhead to pass messages/signalling between the local and remote units. most of registers/bits can be changed while the run bit is set with the following exceptions: ?n_mdsl register ? tx8kssel bit in 17h the mx and dx fifos (mxfiforxt & dxfiforxt) should be reset whenever the pcm or codec clocks are changed while the framer is in the run mode. this will cause an interruption in the payload, but the dsl link will stay up. activation state machine the lxp730 framer has an ansi t1e1.4/94-006 compatible activation state machine. the operation of the state machine is shown in figure 4. figure 4: activation state machine sync & run/ stop = run no sync initial "out-of-sync" state 0 active = 0 los = 1 1 no sync out of sync state 8 active = 0 los = 0 9 sync with no change of frame alignment no sync no sync 7 6 no sync 5 no sync 4 no sync 3 no sync in sync state 2 active = 1 sync no sync sync sync sync sync with change of frame alignment sync cofa = 1 sync (cofa = 0) no sync 10 cofa = 1 no sync
lxp730 application information 15 ) application information typical applications this section shows some block diagrams to serve as example applications. connections to the lxp730 as shown emphasize those relevant for the application. detailed connections to the processor are not shown. figure 5 demonstrates how the lxp730 can simultaneously handle voice from a pcm circuit and packet-type data from an hdlc style device. figure 6 is an example of the hwc mode. the codecs digital interfaces connect directly to the lxp730. an external device is needed to handle signalling information for each voice line supported. in this case the z bits could be used to carry the signalling information such as off-hook status from the cpe and ringing signal from the co. an fpga or a fast dedicated processor could handle these tasks. figure 5: high performance voice/data transport figure 6: pair gain transport lxp730 framer sk70725/21 data pump m p - router pdi pdo pclk pfrm 2.048/4.096 mbps pcm highway tdata rdata quatclk bit_ck lan transceiver lxt905 hdlc microprocessor bus nx64 kbps channels packet/cell data 4 pcm adpi lxp730 framer cdati cdato cclk 2.048 mbps pcm highway frm1 frmn signalling control sio indicators 64 kbps voiceband channels quatclk tdata rdata active bitclk sk70725/21 data pump combo codec combo codec
lxp730 multi-rate dsl framer 16 ) figure 7 shows a more traditional dsl application to carry phone traffic over a longer distance on a single copper pair. the lxp730 supports the pleisiochronous nature of t1/e1 traffic. iom interface circuitry the lxp730 uses a frame pulse in the second cycle of the two clocks per data bit timing. this is directly compatible with the st electrical interface. the iom interfaces use the first clock cycle for the frame pulse. the circuit in figure 8 shows how to adapt the lxp730 to the iom bus. note that even though the circuit is the same for the pcm master or slave modes, there is a difference in the connections to the lxp730 and the iom device. figure 7: t1/e1 fractional transport figure 8: iom adaption circuitry lxp730 framer pdati pdo pclk t1/e1 framer cclk frm1 pfrm microprocessor tdata rdata bitclk quatclk sk70725/21 data pump dq 1/2 74hc74 dq 1/2 74hc74 dq 1/2 74hc74 dq 1/2 74hc74 pfrm pfrm delayed pfrm master pcm frame pclk pclk lxp730 pcm master pcm_fs_pos = 1 lxp730 pcm slave pcm_fs_pos = 0
lxp730 application information 17 ) handling tip/ring reversal in early version of sk70725 the early version of the sk70725 data pump device has an error in the master (co) mode. the quat_clk is not aligned correctly with the rdata for the sign and magnitude bits. when there is no tip/ring reversal, the lxp730 is able to correctly parse the data bits. however, when tip/ring reversal has occurred the lxp730 detects that the sign bit is inverted by detecting the inverted frame sync word (fsw) pattern. the lxp730 then uses the quat_clk to determine which bit to invert. the sign bit is already inverted and the lxp730 inverts the magnitude bit. this problem does not occur in the slave (cpe) mode of the sk70725. the sk70725 has the ability to invert the received data pulses inside itself. this is done by setting bit 7 of the register wr2. the following procedure takes advantage of how the lxp730 reacts during the error condition and the ability to invert the data stream from the sk70725. the procedure uses one of the z-bit bytes after frame sync has been achieved to determine if there is a tip- ring reversal at the ltu. dxz2 and mxz2 are good choices and are used only at the start up time. the tip/ ring reversal indicator in the sk70725 does not have any meaning in mode 0, as the transparent mode needed to work with lxp730. this procedure can be left in the code for the future sk70725 revision. the procedure also shows how to handle belb from the cpe end. tip/ring reversal procedure: 1. start. 2. initialize the lxp730s for required configuration. 3. activate the sk70725s. 4. send the test pattern mxz2 from the ntu side. mxz2 = aah. 5. if dxz2 = aah is received on ltu tip/ring lines are straight and system is ready for transmission. go to step 7. 6. otherwise if dxz2 = 55h, set b7 to 1 in register wr2 of sk70725 (address 02, data 80h). set bit b0 to 0 in register 24h of lxp730 to stop it and then set this bit back to 1 to re-start. the framer needs to be restarted to recognize the new sync word. tip/ring lines are reversed and corrected for in the sk70725, and the system is ready for transmission. 7. normal operation. for belb (back end loop back) on the ntu side: 8. send message to ntu side to set the sk70725 in belb (set bit b6 to 1 in register wr0 of sk70725 on the ntu side). 9. if the tip/ring was detected to be straight then set b4 to 1 in register 17h in ltu lxp730 (address 57h, data 10h) and go to step 11. belb is completed and the system is ready for transmission. 10. if the tip/ring reversal was detected and corrected on the ltu side, then set b7 to 0 in register wr2 of ltu sk70725. set b4 to 1 in register 17 in lxp730 (address 57h, data 10h). set bit b0 to 0 in register 24 of lxp730 to stop it and then set this bit back to 1 to re-start. belb is completed and the system is ready for transmission. 11. when belb testing is done, reset b4 to 1 in register 17h in ltu lxp730 and send the command to ntu to undo belb. before ntu shuts off belb all received payload and overhead data will be scrambled with the wrong polynomial and the value in dxz2 will jump. at the ltu wait until there are two consecutive frames where dxz2 = 55h or aah. 12. go to step 4. dsl system loopbacks data loopbacks in telecom systems are primarily used for system diagnostics. these tests are usually either ber (bit error rate), or to determine which part of the system is malfunctioning. in dsl systems the loopback points are usually controlled by the co (central office) end. line cards may have one or more dsl loops, and the processor on the board sets the loopback operation; typically on command from the central control point in the switching system. the loopback in the linecard demonstrates that the data can successfully be moved from the input at the mx section through the dx section to receive side of the payload. typically this is done with the data pump front end loop back (felb). this transmits the data onto the wire pair, but the receive signal from the wire pair is ignored. instead, the dsl receiver is fed the signal from the transmitter via an internal multiplexer. the framer also has a loop back that ignores data from the data pump. this is useful in isolating the data pump as the source of a malfunction such as when the line has been hit by lightning. a back end loopback (belb) is used to test the wire pair and the remote data pump. here the rdata from the data pump is passed to the framer so it can still receive commands from the co, such as to turn off the belb. a payload loopback at the remote line card will check out the framer and give a more complete evaluation of the dsl system.
lxp730 multi-rate dsl framer 18 ) the co and the cpe each use a different scrambling polynomial in their transmitted data. each side expects to receive a different scrambling setting than the one they transmit. when the framer is in loopback it knows to switch its receive scrambler to match the transmitter. when the local felb is on, the framer does not know by itself that its receive scrambler has to be switched. switching is accomplished in the lxp730 by setting the remote_lb bit in register 17h. this also needs to be done when the remote belb is in operation. when the remote cpe end switches off the belb the co end will not correctly interpret the data until the remote_lb is turned off. however it will still recognize the fsw because it is not scrambled. using multiple devices on an interrupt line the lxp730 int pin is an output pin and therefore requires a circuit, as shown in figure 9, to operate with additional devices that share the same interrupt line to the microprocessor. each lxp730 that is tied to the shared interrupt line will need its own isolating diode. figure 9: multiple interrupt line circuit 1n4148 or equivalent lxp730 int 1n4148 or equivalent lxp730 int interrupt line pull-up +5v int m p to other device interrupt pins
lxp730 test specifications 19 ) test specifications note tables 8 through 23 and figures 10 through 23 represent the performance specifications of the lxp730 and are guaranteed by test except, where noted, by design. the minimum and maximum values listed in tables 10 through 23 are guaranteed over the recommended operating conditions specified in table 9. table anchor - absolute values table anchor - i/o electrical characteristics table 8: absolute maximum ratings parameter symbol min max unit supply voltage v cc -0.3 6 v storage temperature t st -65 +150 oc caution exceeding these values may cause permanent damage. functional operation under these conditions is not implied. exposure to maximum rating conditions for extended periods may affect device reliability. table 9: recommended operating conditions parameter sym min typ 1 max unit recommended supply voltage v cc 4.5 5.0 5.5 v recommended operating temperature t op -40 25 +85 c power dissipation p d -0.30.6 w 1. typical figures are at 25 c and are for design aid only; not guaranteed and not subject to production testing. table 10: i/o electrical characteristics parameter sym min typ 1 max unit test conditions input low voltage v il CC0.3xv cc v cmos inputs input high voltage v ih 0.7xv cc C C v cmos inputs output low voltage v ol CC0.4vi ol = 4 ma output high voltage v oh 0.7xv cc CCvi oh = -4 ma input low current i il -10 C C m av in = gnd, v cc = 5.5v input high current i ih CC10 m av in = v cc , v cc = 5.5v output rise/fall time t r , t f C5Cnsc load = 30 pf capacitance, any input pin c in C12Cpf 1. typical values are at 25 c and are for design aid only; not guaranteed and not subject to production testing.
lxp730 multi-rate dsl framer 20 ) figure 10: generic pcm interface timing table 11: generic pcm bus interface timing specifications (see figure 10) parameter sym min typ 1 max unit test conditions pclk period t cp1 t cp2 122 C 3906 ns pclk duty cycle input 40 C 60 % pclk duty cycle output (mclk) 50 % pclk duty cycle output (adpll) see note 2 pdo delay time t do C C 80 ns pdi setup time t su 20 C C ns pdi hold time t ht 10 C C ns pfrm setup time t fsu 20 C C ns pfrm hold time t fht 10 C C ns pfrm pulse width t fpw 1tcp 1. typical values are at 25 c and are for design aid only; not guaranteed and not subject to production testing. 2. ui jitter = pclk frequency ? mclk frequency. pclk 1 pdi pfrm pdo t do t su pclk 2 t cp1 t cp2 t ch1 t cl1 t cl2 t ch2 t fsu t ht t fht t fpw note: pclk 1 = 1x clock, pclk 2 = 2x clock. clock sampling edges and frame pulse polarity are programmable.
lxp730 test specifications 21 ) figure 11: pcm timing, 1x clock 5 6 7 0 1 2 5 6 7 0 1 2 5 6 7 0 1 2 fe=0, fs_pos=1 dce=0 fe=1, fs_pos=0 fe=1, fs_pos=1 dce=1 dce=1 fe=1, fs_pos=0 fe=1, fs_pos=1 fe=0, fs_pos=0 fe=0, fs_pos=1 data data data 5 6 7 0 1 2 fe=0, fs_pos=0 dce=0 data clocks are shown with arrow indicating sampling edge for data
lxp730 multi-rate dsl framer 22 ) figure 12: pcm timing, 2x clock fe=0, fs_pos=0 dce=0 fe=0, fs_pos=1 dce=0 fe=1, fs_pos=0 fe=1, fs_pos=1 dce=1 dce=1 fe=1, fs_pos=0 fe=1, fs_pos=1 fe=0, fs_pos=0 fe=0, fs_pos=1 data data data data clocks are shown with arrow indicating sampling edge for data 7 0 1 2 3 7 0 1 2 3 7 0 1 2 3 7 0 1 2 3
lxp730 test specifications 23 ) figure 13: codec interface timing table 12: codec interface timing specifications (see figure 13) parameter sym min typ 1 max unit test conditions output delay time of cdato, framesynck t do C C 40 ns referenced from rising edge of cclk codec clock period t cp 122 488 3906 ns cclk duty cycle output (mclk) 50 % cclk duty cycle output (adpll) see note 2 cdati setup t su 20 C C ns referenced from the falling edge of cclk cdati hold time t ht 50 C C ns referenced from the falling edge of cclk 1. typical values are at 25 c and are for design aid only; not guaranteed and not subject to production testing. 2. ui jitter = pclk frequency ? mclk frequency. cdati framesynck 18 7 6 5 4 3 29 cclk cdato t do t su t ht t do t cp t cl t ch
lxp730 multi-rate dsl framer 24 ) figure 14: asynchronous port timing osif sdick t byte_space t d1 t su sdick sdi t ht t d sdock sdo t d2 t byte_space sdock osof t per t per arrows on clocks indicate sampling edge waveforms assume adpi programmed for first two mdsl channels table 13: asynchronous port timing specifications (see fi g ure 14) parameter sym min typ 1 max unit time to next adjacent byte t byte _ space - 8 x bit_clk -1 - seconds clock period t per - mclk -1 x sapclkdiv - seconds delay to first transmit byte t d 1 - 140 x bit_clk -1 - seconds delay to first receive byte t d 2 - 11 x bit_clk -1 - seconds set-up time t su 20 - ns hold time t ht 10 - ns output delay t d -- 40 ns 1. typical figures are at 25 c and are for design aid only; not guaranteed and not subject to production testing.
lxp730 test specifications 25 ) figure 15: osio timing tdata frame 123 11 141516 osif osdick bit_clk 33 rdata frame osof osdock osdi t su t ht t d 2. data waveforms exa g erated with respect to clock to show timin g details more clearly. note: 1. osdick and osdock are shown for oh transparent settin g , and both oh and z bits transported serially table 14: osio timing specifications (see fi g ure 15) parameter sym min typ 1 max unit set-up time t su -- 20 ns hold time t ht 10 -- - output delay t d -- 80 ns 1. typical figures are at 25 c and are for design aid only; not guaranteed and not subject to production testing.
lxp730 multi-rate dsl framer 26 ) figure 16: mdsl interface input timing table anchor - mii 100tx re timing figure 17: mdsl interface output timing bitclk rdata quatclk t su t ht sign bit magnitude bit table 15: mdsl interface input timing specifications ( see fi g ure 16 ) parameter sym min typ 1 max unit test conditions setup time of rdata t su 30 C C ns referenced from falling edge of bitclk hold time of rdata t ht 10 C C ns referenced from falling edge of bitclk 1. typical values are at 25 c and are for design aid only; not guaranteed and not subject to production testing. bitclk tdata t d quatclk sign bit magnitude bit table 16: mdsl interface output timing specifications ( see fi g ure 17 ) parameter sym min typ 1 max unit test conditions output delay time of tdata t d C C 100 ns referenced from rising edge of bitclk 1. typical values are at 25 c and are for design aid only; not guaranteed and not subject to production testing.
lxp730 test specifications 27 ) figure 18: e1/t1 input timing figure 19: e1/t1 output timing table 17: e1/t1 input timing specifications (see figure 18) parameter sym min typ 1 max unit test conditions setup time of t1e1i, frmin t su 30 C C ns referenced from falling edge of pclk hold time of t1e1i, frmin t ht 10 C C ns referenced from falling edge of pclk e1, t1 clock period t pw C488, 647 Cns tclki pulse width low t pwl 50 C C ns tclki pulse width high t pwh 50 C C ns 1. typical values are at 25 c and are for design aid only; not guaranteed and not subject to production testing. t su t pwl t pwh t ht tclki t1e1i, frmin t r t f t pw t d t pwh tclk0 t1e10, frmout t pwl t pw t f t r
lxp730 multi-rate dsl framer 28 ) figure 20: microprocessor write cycle - motorola mode table 19: microprocessor write cycle specificationsmotorola mode (see figure 20) table 18: e1/t1 output timing specifications (see figure 19) parameter sym min typ 1 max unit test conditions output delay time of t1e10, frmout t d C C 100 ns referenced from rising edge of cclk e1, t1 nominal clock period t pw C488, 647 Cns tclk0 pulse width low t pwl 50 C C ns tclk0 pulse width high t pwh 50 C C ns 1. typical values are at 25 c and are for design aid only; not guaranteed and not subject to production testing. parameter sym min typ 1 max unit test conditions address setup time to cs t asu 20 C C ns d<0:7> setup time to cs t dsu 0CCns data-in hold time from cs t dht 10 C C ns allowable cs width t cpw 4/ mclk CCs write hold time t dhw 20 ns 1. typical values are at 25 c and are for design aid only; not guaranteed and not subject to production testing. t asu address (a<0:5>) d<0:7> cs t dsu t cpw t dht r/w t dhw
lxp730 test specifications 29 ) figure 21: microprocessor read cycle - motorola mode table 20: microprocessor read cycle specifications - motorola mode (see figure 21) parameter sym min typ 1 max unit test conditions d<0:7> valid after cs t1 C - 4/mclk s d<0:7> keep valid after cs negation t2 C C 10 ns 1. typical values are at 25 c and are for design aid only; not guaranteed and not subject to production testing. t1 address (a<0:5>) d<0:7> t2 r/w cs
lxp730 multi-rate dsl framer 30 ) figure 22: microprocessor write cycle - intel mode table 21: microprocessor write cycle specificationsintel mode (see figure 22) parameter sym min typ 1 max unit test conditions address setup time t asu 30 C C ns referenced from falling edge of ale address latch enable pulse width t apw 30 ns d<0:7> setup time t wsu 30 C C ns referenced from rising edge of cs or wr d<0:7> hold time t dht 10 C C ns referenced from rising edge of cs or wr cs width t cpw 4/ mclk CCs wr width t wpw 4/ mclk CCs 1. typical values are at 25 c and are for design aid only; not guaranteed and not subject to production testing. t wpw ad<0:7> cs t cpw t dht t wsu wr t asu t apw ale
lxp730 test specifications 31 ) figure 23: microprocessor read cycle - intel mode table 22: microprocessor read cycle specificationsintel mode (see figure 23) table 23: mclk frequency and tolerance specification parameter sym min typ 1 max unit test conditions address setup time t asu 30 C C ns referenced from falling edge of ale address latch enable pulse width t apw 30 C C ns d<0:7> valid after cs , rd assertion t do C C 60 ns referenced from the falling edge of rd and cs d<0:7> keep valid after cs , rd negation t dht C 10 20 ns referenced from rising edge of cs or rd allowed width of cs t cpw 4/ mclk CCs allowed width of rd t rpw 4/ mclk CCs 1. typical values are at 25 c and are for design aid only; not guaranteed and not subject to production testing. parameter sym min typ 1 max unit test conditions mclk frequency f mclk C C 24.832 mhz mclk duty cycle m dc 40C60% 1. typical values are at 25 c and are for design aid only; not guaranteed and not subject to production testing. ad<0:7> cs rd t cpw t rpw ale t do t dht t asu t apw
lxp730 multi-rate dsl framer 32 ) figure 24: reset timing t reset reset table 24: reset timing specifications (see fi g ure 24) parameter sym min typ max unit reset time t reset 3 -- clock periods of slowest externally applied clock
lxp730 register definitions 33 ) register definitions table 25: lxp730 register summary hex address decimal address symbol type description 00 0 n_mdsl r/w number of nx64 channels 01 1 n1 r/w mdsl channel 1 configuration 02 2 n2 r/w mdsl channel 2 configuration 03 3 n3 r/w mdsl channel 3 configuration 04 4 n4 r/w mdsl channel 4 configuration 05 5 n5 r/w mdsl channel 5 configuration 06 6 n6 r/w mdsl channel 6 configuration 07 7 n7 r/w mdsl channel 7 configuration 08 8 n8 r/w mdsl channel 8 configuration 09 9 n9 r/w mdsl channel 9 configuration 0a 10 n10 r/w mdsl channel 10 configuration 0b 11 n11 r/w mdsl channel 11 configuration 0c 12 n12 r/w mdsl channel 12 configuration 0d 13 n13 r/w mdsl channel 13 configuration 0e 14 n14 r/w mdsl channel 14 configuration 0f 15 n15 r/w mdsl channel 15 configuration 10 16 n16 r/w mdsl channel 16 configuration 11 17 n17 r/w mdsl channel 17 configuration 12 18 n18 r/w mdsl channel 18 configuration 13 19 rsvr1 - reserved for future use 14 20 rsvr2 - reserved for future use 15 21 rsvr3 - reserved for future use 16 22 wander r/w wander reduction register 17 23 fifo_misc r/w fifo/miscellaneous control register 18 24 slip_thdl r/w slip buffer threshold low level 19 25 slip_thdh r/w slip buffer threshold high level 1a 26 version r version of the lxp730 1b 27 pllctl1 r/w adpll control 1 1c 28 pllctl2 r/w adpll control 2 1d 29 pllctl3 r/w adpll control 3 1e 30 prog_div r/w mclk divide for pcm/codec blocks
lxp730 multi-rate dsl framer 34 ) 1f 31 idle r/w idle code for blocked pcm and mdsl slots 20 32 pcm1_cfg r/w pcm 1 configurations 21 33 pcm2_cfg r/w pcm 2 configuration 22 34 cod_cfg r/w codec configuration 23 35 misc_ctl r/w miscellaneous control 24 36 ovrhd_cfg r/w overhead mode 25 37 crc_err_cnt r/w crc error counter 26 38 febe_err_cnt r/w febe error counter 27 39 crc_febe_st r/w crc and febe status 28 40 mxoh1 r/w mux overhead bits 1 - 8 29 41 mxoh2 r/w mux overhead bits 9 - 16 2a 42 mxoh3 r/w mux overhead bits 17 - 24 2b 43 mxoh4 r/w mux overhead bits 25 - 32 2c 44 mxz1 r/w mux z bits 1 - 8 2d 45 mxz2 r/w mux z bits 9 - 16 2e 46 mxz3 r/w mux z bits 17 - 24 2f 47 mxz4 r/w mux z bits 25 - 32 30 48 mxz5 r/w mux z bits 33 - 40 31 49 mxz6 r/w mux z bits 41 - 48 32 50 dxoh1 r demux overhead bits 1 - 8 33 51 dxoh2 r demux overhead bits 9 - 16 34 52 dxoh3 r demux overhead bits 17 - 24 35 53 dxoh4 r demux overhead bits 25 - 32 36 54 dxz1 r demux z bits 1 - 8 37 55 dxz2 r demux z bits 9 - 16 38 56 dxz3 r demux z bits 17 - 24 39 57 dxz4 r demux z bits 25 - 32 3a 58 dxz5 r demux z bits 33 - 40 3b 59 dxz6 r demux z bits 41 - 48 3c 60 rsvr4 - reserved for future use table 25: lxp730 register summary C continued hex address decimal address symbol type description
lxp730 register definitions 35 ) number mdsl channels register address: 00 abbreviation: n_mdsl read/write mdsl channel configuration registers (18 bytes) channel 1 address: 01 abbreviation: n1 read/write channel 2 address: 02 abbreviation: n2 read/write 3d 61 rsvr5 - reserved for future use 3e 62 int_en r/w interrupt enables 3f 63 int_status r/w interrupt status flags table 26: number mdsl channels bit name default description <7:5> z_num 0 number of z bits in a group, valid values 0 - 7, number of z bits = z_num + 1. for t1/e1, only z_num = 0 is valid <4:0> number<4:0> 3 number of mdsl channels, valid values: 3 - 17, number of dsl channels = number + 1. table 25: lxp730 register summary C continued hex address decimal address symbol type description table 27: timeslot to channel 1 bit name default description <7,6> ch_cfg 0 channel configuration: 00 codec, 01 idle code, 10 pcm, 11 async data <5:0> ts 0 pcm timeslot, valid values 0 - 63. table 28: timeslot to channel 2 bit name default description <7,6> ch_cfg 0 channel configuration: 00 codec, 01 idle code, 10 pcm, 11 async data <5:0> ts 0 pcm timeslot, valid values 0 - 63.
lxp730 multi-rate dsl framer 36 ) channel 3 address: 03 abbreviation: n3 read/write channel 4 address: 04 abbreviation: n4 read/write channel 5 address: 05 abbreviation: n5 read/write channel 6 address: 06 abbreviation: n6 read/write table 29: timeslot to channel 3 bit name default description <7,6> ch_cfg 0 channel configuration: 00 codec, 01 idle code, 10 pcm, 11 async data <5:0> ts 0 pcm timeslot, valid values 0 - 63. table 30: timeslot to channel 4 bit name default description <7,6> ch_cfg 0 channel configuration: 00 codec, 01 idle code, 10 pcm, 11 async data <5:0> ts 0 pcm timeslot, valid values 0 - 63. table 31: timeslot to channel 5 bit name default description <7,6> ch_cfg 0 channel configuration: 00 codec, 01 idle code, 10 pcm, 11 async data <5:0> ts 0 pcm timeslot, valid values 0 - 63. table 32: timeslot to channel 6 bit name default description <7,6> ch_cfg 0 channel configuration: 00 codec, 01 idle code, 10 pcm, 11 async data <5:0> ts 0 pcm timeslot, valid values 0 - 63.
lxp730 register definitions 37 ) channel 7 address: 07 abbreviation: n7 read/write channel 8 address: 08 abbreviation: n8 read/write channel 9 address: 09 abbreviation: n9 read/write channel 10 address: 0a abbreviation: n10 read/write table 33: timeslot to channel 7 bit name default description <7,6> ch_cfg 0 channel configuration: 00 codec, 01 idle code, 10 pcm, 11 async data <5:0> ts 0 pcm timeslot, valid values 0 - 63. table 34: timeslot to channel 8 bit name default description <7,6> ch_cfg 0 channel configuration: 00 codec, 01 idle code, 10 pcm, 11 async data <5:0> ts 0 pcm timeslot, valid values 0 - 63. table 35: timeslot to channel 9 bit name default description <7,6> ch_cfg 0 channel configuration: 00 codec, 01 idle code, 10 pcm, 11 async data <5:0> ts 0 pcm timeslot, valid values 0 - 63. table 36: timeslot to channel 10 bit name default description <7,6> ch_cfg 0 channel configuration: 00 codec, 01 idle code, 10 pcm, 11 async data <5:0> ts 0 pcm timeslot, valid values 0 - 63.
lxp730 multi-rate dsl framer 38 ) channel 11 address: 0b abbreviation: n11 read/write channel 12 address: 0c abbreviation: n12 read/write channel 13 address: 0d abbreviation: n13 read/write channel 14 address: 0e abbreviation: n14 read/write table 37: timeslot to channel 11 bit name default description <7,6> ch_cfg 0 channel configuration: 00 codec, 01 idle code, 10 pcm, 11 async data <5:0> ts 0 pcm timeslot, valid values 0 - 63. table 38: timeslot to channel 12 bit name default description <7,6> ch_cfg 0 channel configuration: 00 codec, 01 idle code, 10 pcm, 11 async data <5:0> ts 0 pcm timeslot, valid values 0 - 63. table 39: timeslot to channel 13 bit name default description <7,6> ch_cfg 0 channel configuration: 00 codec, 01 idle code, 10 pcm, 11 async data <5:0> ts 0 pcm timeslot, valid values 0 - 63. table 40: timeslot to channel 14 bit name default description <7,6> ch_cfg 0 channel configuration: 00 codec, 01 idle code, 10 pcm, 11 async data <5:0> ts 0 pcm timeslot, valid values 0 - 63.
lxp730 register definitions 39 ) channel 15 address: 0f abbreviation: n15 read/write channel 16 address: 10 abbreviation: n16 read/write channel 17 address: 11 abbreviation: n17 read/write channel 18 address: 12 abbreviation: n18 read/write table 41: timeslot to channel 15 bit name default description <7,6> ch_cfg 0 channel configuration: 00 codec, 01 idle code, 10 pcm, 11 async data <5:0> ts 0 pcm timeslot, valid values 0 - 63. table 42: timeslot to channel 16 bit name default description <7,6> ch_cfg 0 channel configuration: 00 codec, 01 idle code, 10 pcm, 11 async data <5:0> ts 0 pcm timeslot, valid values 0 - 63. table 43: timeslot to channel 17 bit name default description <7,6> ch_cfg 0 channel configuration: 00 codec, 01 idle code, 10 pcm, 11 async data <5:0> ts 0 pcm timeslot, valid values 0 - 63. table 44: timeslot to channel 18 bit name default description <7,6> ch_cfg 0 channel configuration: 00 codec, 01 idle code, 10 pcm, 11 async data <5:0> ts 0 pcm timeslot, valid values 0 - 63.
lxp730 multi-rate dsl framer 40 ) reserved registers (3 bytes) addresses: 13 - 15 abbreviation: rsvr1-3 wander reduction register addresses: 16 abbreviation: wander read/write fifo/miscellaneous control register addresses: 17 abbreviation: fifo_misc read/write table 45: reserved registers bit name default description <7:0> rsrv1-3 - not valid for read or write. table 46: wander reduction register bit name default description <7:0> w_enable 0 0 = disable wander reduction circuit; 24h = enable wander reduction circuit. table 47: fifo/miscellaneous control register bit name default description <7:6> sapclkdiv 00b async serial port clock select, 0 = mclk/2, 1 = mclk/4, 2 = mclk/8, 3 = mclk/16. 5 tx8kssel 0 transmit 8 khz reference sync select control. 0 = tx reference sync selected from pcm interface, 1 = tx reference sync selected from codec interface. 4 remote_lb 0 remote loopback select. controls the scrambling polynomial for remote loopback. 0 = normal operation, 1 = remote loopback. 3 pdoe_sel 0 pcm data output enable select. default value of 0 causes pin to be frmsync12 for codec operation. set to 1 to create the output enable signal pdoe for pcm usage. pdoe goes high for programmed pcm time slots in the nx registers. 2 dxfiforxt 0 dx fifo reset control. the dx elastic store fifo is reset on a 0 to a 1 transition. the 0 or 1 state must be active for a minimum of 3 bitclk periods. 1 mxfiforxt 0 mx fifo reset control. the mx elastic store fifo is reset on a 0 to a 1 transition. the 0 or 1 state must be active for a minimum of 3 bitclk periods. 0 fix2bstuf 0 fixed 2-bit stuffing mode enable; 0 = disable, 1 = enable.
lxp730 register definitions 41 ) slip buffer lower threshold register address: 18 abbreviation: slp_thdl read/write slip buffer upper threshold register address: 19 abbreviation: slp_thdh read/write version register address: 1a abbreviation: version read only table 48: slip buffer lower threshold bit name default description <7> slp_l_en 0 0 = use default, 1 = enable and use bits <6:0> for the lower threshold. must be set when stopped (run/stop = 0). <6:0> slp_lwr 0 mpc mode: lower threshold of pcm receive slip buffer (default 31- n). hwc mode: not used. table 49: slip buffer upper threshold bit name default description <7> slp_u_en 0 0 = use default, 1 = enable and use bits <6:0> for the upper threshold. must be set when stopped (run/stop = 0). <6:0> slp_upr 0 mpc mode: upper threshold of pcm receive slip buffer (default 32+n). hwc mode: not used. table 50: version bit name default description <7:0> ver 0 version of device.
lxp730 multi-rate dsl framer 42 ) internal clock control registers (4 bytes) adpll control 1 address: 1b abbreviation: pllctl1 read/write adpll control 2 address: 1c abbreviation: pllctl2 read/write adpll control 3 address: 1d abbreviation: pllctl3 read/write mclk divide address: 1e abbreviation: prog_div read/write table 51: adpll control 1 bit name default description <7:0> cfreq(17:10) 40 center frequency of the adpll. table 52: adpll control 2 bit name default description <7:0> cfreq(9:2) 0 center frequency of the dppl. table 53: adpll control 3 bit name default description <7:6> cfreq(1:0) 0 center frequency of the dppl. <5> auto_rst 0 1 = the adpll automatically resets the rx fifo after lock. 0 = no reset. <4:0> kloop(4:0) 9 adpll loop filter gain setting. table 54: prog divide bit name default description <7:0> prog_div 07 prog divide, pre-scaler for pcm and codec interfaces, prescaleout = mclk/(mclk_div + 1).
lxp730 register definitions 43 ) programmable idle code byte address: 1f abbreviation: idle read/write pcm configuration registers pcm1 configuration address: 20 abbreviation: pcm_cfg1 read/write table 55: programmable idle code byte bit name default description <7:0> idle <7:0> ffh programmable idle code. this 8 bit code contains the bit used for channel blocking. table 56: pcm 1 configuration bits bit name default description 7 pclkmode 0 set to 0 for 1x clock, set to 1 for 2x clock. <6:5> pclkmux 10b pcm clock mux 00 external pin, pclk pin-14 (pcm slave) 01 internal adpll (pcm master) 10 mclk divided by prog_div register 11 adpll output divided by prog_div register 4 dce 0 data clock edge, 0 = sample input data on falling edge - output data on rising edge, 1 = sample input on rising edge - output data on falling edge. 3 finv 0 frame sync pulse polarity, 0 = active low, 1 = active high. 2 fe 0 frame clock edge, 0 = sample frame sync on falling edge - output on rising edge, 1 = sample frame sync on rising edge - output on falling edge. 1 sbbp 1 slip buffer bypass, 0 = slip buffer active, 1 = slip buffer bypassed. 0 tfi 0 tri-state for idle code, 0 = pass idle to pcm, 1 = tri-state pcm for idle.
lxp730 multi-rate dsl framer 44 ) pcm2 configuration address: 21 abbreviation: pcm_cfg2 read/write codec configuration register address: 22 abbreviation: cod_cfg read/write table 57: pcm 2 configuration bits bit name default description 7 t1e1/pcm 0 t1e1 - pcm selection, 0 = pcm mode, 1 = t1e1 mode. 6 t1e1 1 t1/e1 selection, 0 = t1 frame mode, 1 = e1 frame mode. <5:0> maxpchn 1fh max number of pcm channels, values 0 - 63, maxpchn + 1 = n pcm channels between pcm sync pulses. table 58: codec configuration bit name default description <7:6> cclkmux 10b codec clock mux 00 external pin, pclk pin-14 01 internal adpll 10 mclk divided by prog_div register 11 adpll output divided by prog_div register <0:5> maxcchn 1fh max number of codec channels, values 0 - 31, maxcchn + 1 = n codec channels between codec sync pulses.
lxp730 register definitions 45 ) overhead registers (25 bytes) miscellaneous control address: 23 abbreviation: misc_ctl read/write overhead configuration address: 24 abbreviation: ovrhd_cfg read/write table 59: miscellaneous control bit name default description <7:6> los_sel 00b los select, for outgoing mx direction 00 set los based on pclk 01 set los based on codec clock 10 disable los; set 1 to losd on tx dsl frame 11 enable los, for testing; set 0 to losd on tx dsl frame 5 cclkmode 0 set to 0 for 1x clock, set to 1 for 2x clock. 4 gap_clk 0 gapped dsl clock out select, enable output for gapped receive dsl clock. 0 = output always high, 1 = gapped clock out. 3 z_ctl 0 z bit mux control, 1 = z bits to registers (z_num = 0 only), 0 = z bits to osio. 2 aspsel 0 adpi serial port select enable. 0 = disabled, 1 = enabled. enabling the adpi disables codec frame syncs 7, 8, 9, and 10. 1 cclk_oe 0 codec clock output enable. 0 = disabled, 1 = enabled. 0 pcm_fs_pos 1 pcm frame sync position: 0 = first bit of the frame, 1= last bit of the frame. table 60: overhead configuration bit name default description 7 par/ser 0 overhead data mode: set to 0 for external pins, 1 for internal register. 6 trans/predef 0 1 for transparent mode, 0 for limited pre-defined mode. 5 crc_cnt 0 crc-6 error counter mode: 0 for reset when read, 1 for modulo count. 4 febe_cnt 0 febe error counter mode: 0 for reset when read, 1 for modulo count. 3 l/r 0 local/remote mode, 0 for remote, 1 for local, selects scrambling polynomial. 2 src_en 0 scrambler enable, 0 enabled, 1 disabled. 1 dsl_lb 0 dsl interface loop back, 0 disabled, 1 enabled. 0 run/stop 0 0 = set mdsl framer state machine to deactivated state, 1 = set mdsl framer state machine to activation state.
lxp730 multi-rate dsl framer 46 ) crc error counter address: 25 abbreviation: crc_err_cnt read/write febe error counter address: 26 abbreviation: febe_err_cnt read/write crc - febe - los status address: 27 abbreviation: crc_febe_st read/write table 61: crc error counter bit name default description <7:0> crc_err_ cnt <7:0> 0 crc error counter, mode set by crc mode bit in ovrhd_cfg register. table 62: febe error counter bit name default description <7:0> febe_err_ cnt <7:0> 0 febe error counter, mode set by febe mode bit in ovrhd_cfg register. table 63: crc - febe status bit name default description 7 crc_ovr 0 1 when crc error counter overflowed in reset mode. must write 1 to reset. 6 febe_ovr 0 1 when febe error counter overflowed in reset mode. must write 1 to reset. 5 crcerrinj 0 crc error injection; when this bit is set to 1 a crc will be injected, then the lxp730 will clear this bit after 1 dsl frame. 4 mx_los 0 1 when los occurs, affected by los_sel in misc_ctl. <3:1> n/a 000b reserved. 0 dslactive 0 dsl link active status -- reports current status.
lxp730 register definitions 47 ) mx overhead bits 1 - 8 address: 28 abbreviation: mxoh1 read/write mx overhead bits 9 - 16 address: 29 abbreviation: mxoh2 read/write mx overhead bits 17 - 24 address: 2a abbreviation: mxoh3 read/write table 64: mx overhead bits 1 - 8 bit name default description 7 mx8/crc2 0 transparent mode/ pre defined mode. 6 mx7/crc1 0 transparent mode/ pre defined mode. <5:2> mx<6:3> 00b user definable. 1 mx2/febe 0 transparent mode/ pre defined mode. 0 mx1/los 0 transparent mode/ pre defined mode. table 65: mx overhead bits 9 - 16 bit name default description <7:0> mx<16:9> 0 user definable. table 66: mx overhead bits 17 - 24 bit name default description <7:2> mx<24:19> 0 user definable. 1 mx18/crc4 0 transparent mode/ pre defined mode. 0 mx17/crc3 0 transparent mode/ pre defined mode.
lxp730 multi-rate dsl framer 48 ) mx overhead bits 25 - 32 address: 2b abbreviation: mxoh4 read/write mx z bits 1 - 8 address: 2c abbreviation: mxz1 read/write mx z bits 9 - 16 address: 2d abbreviation: mxz2 read/write mx z bits 17 - 24 address: 2e abbreviation: mxz3 read/write table 67: mx overhead bits 25 - 32 bit name default description <7:6> mx<32,31> 00b user definable. 5 mx30/indcr 0 transparent mode/ pre defined mode. 4mx290user definable. 3 mx28/crc6 0 transparent mode/ pre defined mode. 2 mx27/crc5 0 transparent mode/ pre defined mode. <0:1> mx<25,26> 00b user definable. table 68: mx z bits 1 - 8 bit name default description <7:0> mxz<8:1> 0 user definable when not in t1 mode. table 69: mx z bits 9 - 16 bit name default description <7:0> mxz<16:9> 0 user definable when not in t1 mode. table 70: mx z bits 17 - 24 bit name default description <7:0> mxz<17:24> 0 user definable when not in t1 mode.
lxp730 register definitions 49 ) mx z bits 25 - 32 address: 2f abbreviation: mxz4 read/write mx z bits 33 - 40 address: 30 abbreviation: mxz5 read/write mx z bits 41 - 48 address: 31 abbreviation: mxz6 read/write dx overhead bits 1 - 8 address: 32 abbreviation: dxoh1 read/write table 71: mx z bits 25 - 32 bit name default description <7:0> mxz<32:25> 0 user definable when not in t1 mode. table 72: mx z bits 33 - 40 bit name default description <7:0> mxz<40:33> 0 user definable when not in t1 mode. table 73: mx z bits 41 - 48 bit name default description <7:0> mxz<48:41> 0 user definable when not in t1 mode. table 74: dx overhead bits 1 - 8 bit name default description 7 dx8/crc2 0 transparent mode/ pre defined mode. 6 dx7/crc1 0 transparent mode/ pre defined mode. <5:2> dx<6:3> 0000b user definable. 1 dx2/febe 0 transparent mode/ pre defined mode. 0 dx1/los 0 transparent mode/ pre defined mode.
lxp730 multi-rate dsl framer 50 ) dx overhead bits 9 - 16 address: 33 abbreviation: dxoh2 read/write dx overhead bits 17 - 24 address: 34 abbreviation: dxoh3 read/write dx overhead bits 25 - 32 address: 35 abbreviation: dxoh4 read/write dx z bits 1 - 8 address: 36 abbreviation: dxz1 read/write table 75: dx overhead bits 9 - 16 bit name default description <7:0> dx<16:9> 0 user definable. table 76: dx overhead bits 17 - 24 bit name default description <7:2> dx<24:19> 0 user definable. 1 dx18/crc4 0 transparent mode/ pre defined mode. 0 dx17/crc3 0 transparent mode/ pre defined mode. table 77: dx overhead bits 25 - 32 bit name default description <7:6> dx<32,31> 00b user definable. 5 dx30/indcr 0 transparent mode/ pre defined mode. 4 dx29 0 user definable. 3 dx28/crc6 0 transparent mode/ pre defined mode. 2 dx27/crc5 0 transparent mode/ pre defined mode. <0:1> dx<25,26> 00b user definable. table 78: dx z bits 1 - 8 bit name default description <7:0> dxz<8:1> 0 user definable when not in t1 mode.
lxp730 register definitions 51 ) dx z bits 9 - 16 address: 37 abbreviation: dxz2 read/write dx z bits 17 - 24 address: 38 abbreviation: dxz3 read/write dx z bits 25 - 32 address: 39 abbreviation: dxz4 read/write dx z bits 33 - 40 address: 3a abbreviation: dxz5 read/write dx z bits 41 - 48 address: 3b abbreviation: dxz6 read/write table 79: dx z bits 9 - 16 bit name default description <7:0> dxz<16:9> 0 user definable when not in t1 mode. table 80: dx z bits 17 - 24 bit name default description <7:0> dxz<17:24> 0 user definable when not in t1 mode. table 81: dx z bits 25 - 32 bit name default description <7:0> dxz<32:25> 0 user definable when not in t1 mode. table 82: dx z bits 33 - 40 bit name default description <7:0> dxz<40:33> 0 user definable when not in t1 mode. table 83: dx z bits 41 - 48 bit name default description <7:0> dxz<48:41> 0 user definable when not in t1 mode.
lxp730 multi-rate dsl framer 52 ) reserved registers (2 bytes) addresses: 3c and 3d abbreviation: rsvr4 and 5 interrupt registers (2 bytes) interrupt enables address: 3e abbreviation: int_en read/write interrupt status address: 3f abbreviation: int_stat read/write table 84: reserved registers bit name default description <7:0> rsrv4,5 - not valid for read or write. table 85: interrupt enables bit name default description 7 los_en 0 loss of source interrupt enable (set to 1 to enable). 6 crc_febe_en 0 crc - febe interrupt enable. 5 indcr_en 0 indcr interrupt enable. 4 slip_det_ en 0 slip detect interrupt enable. 3 ohmx_en 0 overhead mx interrupt enable. 2 ohdx_en 0 overhead dx interrupt enable. 1 active_en 0 active interrupt enable. 0 cofa_en 0 cofa interrupt enable. table 86: interrupt status bit name default description 7 los 0 loss of source interrupt, set to 1 when los is received in dx1/los. 6 crc_febe 0 crc - febe interrupt, set to 1 when 1.) crc error is detected in dx, or 2.) febe is received in dx2/febe. 5 indcr 0 indcr interrupt, set to 1 when indcr is received in dx30/indcr. 4 slip_det 0 slip detect interrupt, set to 1 when slip occurs in slip buffer. 3 ohmx 0 overhead mx interrupt, set to 1 when mx frame has started allowing 6ms to write mx registers before start of next frame. 2 ohdx 0 overhead dx interrupt, set to 1 when dx frame has ended allowing 6ms to read dx registers before end of next frame. 1 active 0 active interrupt, set to 1 when mdsl link is up. 0 cofa 0 cofa interrupt, set to 1 when change of frame position occurs.
lxp730 mechanical specifications 53 ) mechanical specifications figure 25: 64 - pin lqfp package specification d d 1 e e 1 for sides with even number of pins e / 2 for sides with odd number of pins e a 1 a 2 l a b l 1 q 3 q 3 q part number LXP730LE ? 64-pin low profile quad flat pack ? extended temperature range (-40 to +85 c) dim inches millimeters min max min max a .063 C 1.60 a 1 .002 .006 0.05 0.15 a 2 .053 .057 1.35 1.45 b.007.0110.17 0.27 d0.472 bsc 1 12.00 bsc 1 d 1 0.394 bsc 1 10.00 bsc 1 e0.472 bsc 1 12.00 bsc 1 e 1 0.394 bsc 1 10.00 bsc 1 e0.020 bsc 1 0.50 bsc 1 l 0.018 0.030 0.45 0.75 l 1 0.039 ref 1.00 ref q 3 11 13 11 13 q 0 7 0 7
lxp730 multi-rate dsl framer 54 ) revision history this section provides a listing of changes between revisions. this revision history assumes rev 1.0 as the baseline. table 87: changes from previous revision (rev 1.0) to current document (rev 2.0) section page change description features 1 inserted "payload features 1 inserted: "the " features 1 replaced: "interface in both directions" with: "interface" features 1 inserted: "slave mode: external clock determines ..." features 1 replaced: "clock" with: "clock or external oscillator" features 1 deleted: "slave mode: external clock determines table 1 - pin 28 2 replaced: "i/" with: "di/" table 1 - pin 28 2 replaced: "o" with: "do" table 1 - pin 29 2 replaced: "i/" with: "di/" table 1 - pin 29 2 replaced: "o" with: "do" table 1 - pin 30 2 replaced: "i/" with: "di/" table 1 - pin 30 2 replaced: "o" with: "do" table 1 - pin 31 2 replaced: "i/" with: "di/" table 1 - pin 31 2 replaced: "i" with: "di" table 1 - pin 34 2 replaced: "i/" with: "di/" table 1 - pin 34 2 replaced: "o" with: "do" table 1 - pin 35 3 replaced: "i/" with: "di/" table 1 - pin 35 3 replaced: "o" with: "do" table 1 - pin 36 3 replaced: "i/" with: "di/" table 1 - pin 36 3 replaced: "o" with: "do" table 1 - pin 37 3 replaced: "i/" with: "di/" table 1 - pin 37 3 replaced: "o" with: "do" table 1 - pin 22 3 replaced: "i, 0" with: "di, do" table 1 - pin 23 3 replaced: "i" with: "di" table 1 - pin 24 3 replaced: "i" with: "di" table 1 - pin 25 3 replaced: "i" with: "di" table 1 - pin 26 3 replaced: "i" with: "di" table 1 - pin 27 3 replaced: "i, 0" with: "di, do" table 1 - pin 57 3 replaced: "i" with: "di" table 1 - pin 39 3 replaced: "i" with: "di" table 1 - pin 38 3 replaced: "i" with: "di" table 1 - pin 41 3 replaced: "i" with: "di"
lxp730 revision history 55 ) table 1 - pin 42 3 replaced: "od" with: "do" table 1 - pin 42 3 replaced: "interrupt, open drain. with: "interrupt output. table 1 - pin 56 3 replaced: "i" with: "di" table 1 - pin 8 3 replaced: "i' with: "di" table 1 - pin 4 3 replaced: "i" with: "di" table 1 - pin 5 3 replaced: "o" with: "do" table 1 - pin 6 3 replaced: "o" with: "do" table 1 - pin 7 3 replaced: "o" with: "do" table 1 - pin 62 3 replaced: "o" with: "do" table 1 - pin 61 3 replaced: "o" with: "do" table 1 - pin 60 3 replaced: "o" with: "do" table 1 - pin 59 4 replaced: "o" with: "do" table 1 - pin 58 4 replaced: "o" with: "do" table 1 - pin 54 4 replaced: 6'0, i" with: "do, di" table 1 - pin 53 4 replaced: "o" with: "do" table 1 - pin 52 4 replaced: "o" with: "do" table 1 - pin 51 4 inserted: "o" with: "do" table 1 - pin 14 4 replaced: "i/" with: "di" pcm-interface 6 replaced: iom2 " with: "iom2 (see figure 8 pcm-interface 6 inserted: "there is a limitation of ..." overhead serial i/o 8 replaced: "bits with: "bits (plus the indc-r bit) mdsl overhead 8 replaced: "sel with: "ser " mdsl overhead 8 replaced: "reset" with: "set mdsl overhead 8 inserted: "the registers for the oh adpll performance 9 replaced: "the " with: "as shown in table 3... adpll performance 9 replaced: "bandwidth " with: "bandwidth (bw) typical application 15 inserted: "figure 6 is an - - - " figure 6 15 replaced: "figure 6 is an ..." with: "pair gain transport" typical application 16 inserted: "iom interface circuitry... " figure 6 16 inserted: "iom adaption circuitry..." handling tip/ring 17 inserted: handling tip/ring..... handling tip/ring 17 inserted: dsl system loopbacks figure 9 18 inserted: multiple interrupt line circuitry table 11 19 inserted: "recommended in title figure 11 21 replaced: "generic pcm-bus signal alignment..." with:"pcm timing, 1 x clock figure 12 22 inserted: "pcm timing, 2 x clock table 87: changes from previous revision (rev 1.0) to current document (rev 2.0) C continued section page change description
lxp730 multi-rate dsl framer 56 ) figure 14 24 inserted: "asynchronous port timing..." figure 15 25 inserted osio timing spec...... figure 20 28 inserted: "microprocessor write cycle - motorola mode..." table 20 28 inserted: "microprocessor write cycle - motorola mode..." figure 21 29 replaced: "write " with: "read " table 20 29 replaced: "write " with: "read " figure 22 30 replaced: "read cycle - motorola " with: "write cycle -intel " table 21 30 replaced: "read " with: "write figure 23 31 replaced: "write " with: "read table 22 31 replaced: "write " with: "read table 22 31 replaced: "d<0:7> setup time" with: "d<0:7> valid after table 22 31 replaced: twsu" with: "tdo" table 22 31 replaced: "30" with: "-" table 22 31 replaced: "-" with: "60" table 22 31 replaced: "rising " with: "the falling table 22 31 replaced: "cs or wr" with: "rd and cs" table 22 31 replaced: "d<0:7> hold time"with: "d<0:7> keep valid..." table 22 31 replaced: "tdht" with: "tdht" table 22 31 replaced: "10" with: "-" table 22 31 replaced: "-" with: "10" table 22 31 replaced: "-" with: "20" table 22 31 replaced: "nm" with: "rd" table 22 31 replaced: " cs width" with: "allowed width of cs" table 22 31 replaced: " wr width" with: "allowed width of rd" table 22 31 replaced: "twpw" with: " trpw " figure 24 32 inserted: reset timing table 87: changes from previous revision (rev 1.0) to current document (rev 2.0) C continued section page change description
lxp730 notes 57 ) notes
lxp730 multi-rate dsl framer 58 ) notes
lxp730 notes 59 ) notes
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